中国邮电高校学报(英文) ›› 2011, Vol. 18 ›› Issue (6): 122-126.doi: 10.1016/S1005-8885(10)60130-6

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Jitter analysis and modeling of a 10 Gbit/s SerDes CDR and jitter attenuation PLL

WANG Hui1,陈莹梅, YI Lv-fan2, WEN Guan-guo2   

  1. 1. Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China 2. Zhongxing Telecom Equipment Corporation, Shenzhen 518055, China
  • 收稿日期:2011-04-16 修回日期:2011-08-21 出版日期:2011-12-31 发布日期:2011-12-30
  • 通讯作者: WANG Hui E-mail: njcym@seu.edu.cn
  • 基金资助:

    This work was supported by the National Natural Science Foundation of China (60976029), and the Research Foundation of Zhongxing Telecom Equipment Corporation.

Jitter analysis and modeling of a 10 Gbit/s SerDes CDR and jitter attenuation PLL

1. Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China 2. Zhongxing Telecom Equipment Corporation, Shenzhen 518055, China   

  • Received:2011-04-16 Revised:2011-08-21 Online:2011-12-31 Published:2011-12-30
  • Contact: WANG Hui E-mail: njcym@seu.edu.cn
  • Supported by:

    This work was supported by the National Natural Science Foundation of China (60976029), and the Research Foundation of Zhongxing Telecom Equipment Corporation.

摘要:

Jitter analysis and a linear model is proposed in this paper which predicts the characteristics of serial-deserial (SerDes) clock and data recovery circuit, and the characteristics include jitter transfer, jitter tolerance and jitter generation are particularly analyzed. The simulation results of the clock data recovery (CDR) model show that the jitter specifications exceed the mask of ITU-T optical transport network (OTN) G.8251 recommendations. The whole systems are validated by 9.95–11.5 Gbit/s CDR and the jitter attenuation phase locked loops (PLL) circuits using TSMC 65 nm CMOS technology.

关键词:

OTN, SerDes, Jitter, CDR, PLL

Abstract:

Jitter analysis and a linear model is proposed in this paper which predicts the characteristics of serial-deserial (SerDes) clock and data recovery circuit, and the characteristics include jitter transfer, jitter tolerance and jitter generation are particularly analyzed. The simulation results of the clock data recovery (CDR) model show that the jitter specifications exceed the mask of ITU-T optical transport network (OTN) G.8251 recommendations. The whole systems are validated by 9.95–11.5 Gbit/s CDR and the jitter attenuation phase locked loops (PLL) circuits using TSMC 65 nm CMOS technology.

Key words:

OTN, SerDes, Jitter, CDR, PLL